Considering a programmable logic device (PLD) as one example of an integrated circuit device, as applications for which PLDs are used increase in complexity, it has become more common to design PLDs to include configurable specialized processing blocks in addition to blocks of generic programmable logic resources. Such configurable specialized processing blocks may include a concentration of circuitry on a PLD that has been partly or fully hardwired to perform one or more specific tasks, such as a logical or a mathematical operation. A configurable specialized processing block may also contain one or more specialized structures, such as an array of configurable memory elements. Examples of structures that are commonly implemented in such configurable specialized processing blocks include: adders/subtractors, arithmetic logic units (ALUs), barrel-shifters, various memory elements (such as FIFO/LIFO/SIPO/RAM/ROM/CAM blocks and register files), AND/NAND/OR/NOR arrays, etc., or combinations thereof.
One particularly useful type of configurable specialized processing block that has been provided on PLDs is a digital signal processing (DSP) block, which may be used to process, e.g., audio signals. Such blocks are frequently also referred to as multiply-accumulate (“MAC”) blocks, because they include structures to perform multiplication operations, and sums and/or accumulations of multiplication operations.
For example, PLDs sold by Altera Corporation, of San Jose, Calif., as part of the STRATIX® and ARRIA® families include DSP blocks, each of which includes a plurality of multipliers, adders/subtractors, and registers, as well as programmable connectors (e.g., multiplexers) that allow the various components of the block to be configured in different ways.
Floating Point Compiler (FPC) technology has been developed to map floating point datapaths to generic PLD (and other integrated circuit) architectures, which may include DSP blocks, as described above. Aspects of such FPC technology may be found described in commonly-assigned U.S. patent application Ser. No. 11/625,655 (now U.S. Pat. No. 7,865,541), filed Jan. 22, 2007, which is hereby incorporated by reference herein in its entirety. FPC may achieve efficiency gains by fusing together large subsections of a datapath, for example, by clustering similar operations together, and by optimizing the interface between clusters of dissimilar operators. Using Floating Point Compiler (FPC) technology to perform calculations may be important to Altera's DSP offering. Such FPC technology may be used for calculating the sum or product of two double precision numbers. For example, the MATH.H library used in the C/C++ programming languages requires compliant systems to support of double precision multiplication.
The IEEE754 1985 standard is commonly used for floating point numbers. A floating point number includes three different parts: the sign of the number, its mantissa and its exponent. The mantissa may be of different sizes, depending on the desired precision of the floating point number. For example, the mantissa may be 23 bits long for single precision floating point numbers, with an implied leading 1. For example, the mantissa may be 52 bits long for double precision floating point numbers, with an implied leading 1. In comparison with calculations in accordance with the IEEE754 1985 standard, FPC technology may produce higher quality results. In particular, 75% of FPC based calculations may be more accurate than the equivalent calculations performed using the IEEE754 1985 standard. This may be because FPC based calculations may support larger average mantissas and may provide local underflow and overflow support. FPC based calculations may make use of mantissas of a similar size to the IEEE754-1985 standard, but may not round to the same sizes of mantissas as specified in the IEEE754 1985 standard. For example, even if the FPC based calculations are to be the analog of calculations of the IEEE754 1985 standard in terms of precision, single precision FPC based calculations may make use of larger mantissas, e.g., 32 bit mantissas. As another example, single precision FPC based calculations may make use of mantissas of variable sizes, e.g., 24 bits or larger mantissas. However, 25% of FPC based calculations may be less accurate than the equivalent calculations performed using the IEEE754 1985 standard. This may be because of a lack of rounding of numbers, which may be due to the difficulty of inserting/supporting sticky bits in current FPC signed number formats. Specifically, rounding numbers based on the FPC technology may be expensive in terms of the need to include additional mantissa adder structure, which could lead to increased clock latency and an increase in floating point adder area, e.g., by 15%. In addition, rounding numbers based on FPC technology may be expensive due to an absolute value (ABS) calculation performed, after addition using the added mantissa adder structure, and the possible further increased clock latency that results from this ABS calculation. In addition, the use of unsigned numbers in an FPC may be costly in terms of efficiency for the FPC, which primarily makes use of signed non-normalized numbers.